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HT23C512 cmos 64k 8-bit mask rom block diagram rev. 1.10 1 august 30, 2002 features operating voltage: 2.7v~5.5v low power consumption operation: 25ma max. (v cc =5v) 10ma max. (v cc =3v) standby: 30 a max. (v cc =5v) 10 a max. (v cc =3v) access time: 150ns max. (v cc =5v) 250ns max. (v cc =3v) 65536 8-bit of mask rom mask options: chip enable ce/ce /oe1/oe1 and output enable oe/oe /nc ttl compatible inputs and outputs tristate outputs fully static operation 28-pin dip/sop package general description the HT23C512 is a read-only memory with high perfor - mance cmos storage device whose 512k of memory is arranged into 65536 words by 8 bits. for application flexibility, the chip enable and output en - able control pins can be selected as active high or active low. this flexibility not only allows easy interface with most microprocessors, but also eliminates bus conten - tion in multiple bus microprocessor systems. an addi - tional feature of the HT23C512 is its ability to enter the standby mode whenever the chip enable (ce/ce )isin - active, thus reducing current consumption to below 30 a. the combination of these functions makes the chip suitable for high density low power memory appli - cations.
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pin assignment pin description pin name i/o description a0~a15 i address inputs d0~d7 o data outputs ce/ce /oe1/oe1 i chip enable/output enable input oe/oe /nc i output enable input vss negative power supply, ground vcc positive power supply absolute maximum ratings supply voltage ............................................ 0.3v to 6v storage temperature ............................ 50 cto125 c input voltage.................................... 0.3v to v cc +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics supply voltage: 2.7v~3.6v ta = 40 cto85 c symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage 2.7 3.6 v i cc operating current 3v o/p unload, f=5mhz 10 ma v il input low voltage 3v v ss 0.4 v v ih input high voltage 3v 2.0 v cc v v ol output low voltage 3v i ol =2.1ma 0.4 v v oh output high voltage 3v i oh = 0.4ma 2.4 v cc v HT23C512 rev. 1.10 2 august 30, 2002
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symbol parameter test conditions min. typ. max. unit v cc conditions i li input leakage current 3v v in =0 to v cc 10 a i lo output leakage current 3v v out =0 to v cc 10 a i stb1 standby current 3v ce=v il ,ce =v ih 500 a i stb2 standby current 3v ce 0.2v, ce v cc 0.2v 10 a c in input capacitance (see note) f=1mhz 10 pf c out output capacitance (see note) f=1mhz 10 pf note: these parameters are periodically sampled but not 100% tested. supply voltage: 4.5v~5.5v ta = 40 cto85 c symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage 4.5 5.5 v i cc operating current 5v o/p unload, f=5mhz 25 ma v il input low voltage 5v v ss 0.8 v v ih input high voltage 5v 2.2 v cc v v ol output low voltage 5v i ol =3.2ma 0.4 v v oh output high voltage 5v i oh = 1ma 2.4 v cc v i li input leakage current 5v v in =0 to v cc 10 a i lo output leakage current 5v v out =0 to v cc 10 a i stb1 standby current 5v ce=v il ,ce =v ih 1.5 ma i stb2 standby current 5v ce 0.2v, ce v cc 0.2v 30 a c in input capacitance (see note) f=1mhz 10 pf c out output capacitance (see note) f=1mhz 10 pf note: these parameters are periodically sampled but not 100% tested. a.c. characteristics ta = 40 cto85 c symbol parameter v cc =2.7v~3.6v v cc =4.5v~5.5v unit min. max. min. max. t cyc cycle time 250 150 ns t aa address access time 250 150 ns t ace chip enable access time 250 150 ns t aoe output enable access time 150 80 ns t oh output hold time 10 ns t od output disable time (see note) 70 ns t oe output enable time (see note) 10 ns note: these parameters are periodically sampled but not 100% tested. HT23C512 rev. 1.10 3 august 30, 2002
a.c. test conditions output load: see figure right input rise and fall time: 10ns input pulse levels: 0.4v to 2.4v input and output timing reference levels: 0.8v and 2.0v (v cc =5v), 1.5v (v cc =3v) operation truth table mode ce/ce oe/oe a0~a15 d0~d7 read h/l h/l valid data out deselect h/l l/h x high z standby l/h x x high z note: h=v ih , l=v il , x=v ih or v il timing diagrams propagation delay due to address (ce/ce /oe1/oe1 and oe/oe are active) propagation delay due to chip enable and output enable (address valid) HT23C512 rev. 1.10 4 august 30, 2002 # 0 1 ' - ( ( $ % # % 1 2 % + # 3 + 4 output load circuit functional description the HT23C512 has two modes, namely data read mode and standby mode, controlled by ce/ce /oe1/oe1 and oe/oe /nc inputs. standby mode the HT23C512 has lower current consumption, con - trolled by the chip enable input (ce/ce ). when a low/high level is applied to the ce/ce input regardless of the output enable (oe/oe /nc) states, the chip will enter the standby mode. data read mode when both the chip enable (ce/ce /oe1/oe1 ) and the output enable (oe/oe /nc) are active, the chip is in data read mode. otherwise, active ce/ce and inac - tive oe/oe /nc result in deselect mode. the output will remain in hi-z state. ' 3 + + + % ' 3 + $ 5 ) ) $ ) $ ) ) $ ) $ % ' 3 + )
characteristic curves HT23C512 rev. 1.10 5 august 30, 2002 6 6 / 6 6 - 6 . 6 - - ( ! " 6 6 ( 6 / 6 6 . 6 6 6 ! # $ % ! " 6 6 / 6 6 - 6 . 6 - - ( ! # $ % ! " 6 / 6 / 6 6 6 6 & & ' ' ! " 6 ( 6 6 / 6 6 6 - - - ( & & ' ' ! " 6 6 ( 6 / 6 6 . 6 6 6 ! " ( ( ( " " ' 7 ' 8 3 7 - ( ( ( " " ' 7 ' 8 3 7 - ( ( ( " " ' 7 ' 8 3 7 -
HT23C512 rev. 1.10 6 august 30, 2002 6 / 6 / 6 6 6 6 & & ' ' ) ! " 6 ( 6 6 / 6 6 6 - - - ( & & ' ' ) ! " 6 / 6 / 6 6 6 6 & & ' ' ) ! " 6 ( 6 6 / 6 6 6 - - - ( & & ' ' ) ! " ( ( ( " " ' 7 ' 8 3 7 - ( ( ( " " ' 7 ' 8 3 7 -
HT23C512 mask rom ordering sheet custom: input medium: eprom disk file (mail address: romfile@holtek.com.tw) other user no. type/ref. name q'ty check sum memory address start end control pin and package form option: (a) 28 pin type pin 20: (1) ce (2) ce (3) oe1 (4) oe1 pin 22: (1) oe (2) oe (3) nc (b) package form: (1) chip form (2) 28 dip (3) 28 sop companion user no. package marking : delivery date : q'ty : custom confirmed by: (name, date, position & co. chop) holtek confirmed by: (sales) (sales manager) HT23C512 rev. 1.10 7 august 30, 2002
package information 28-pin dip (600mil) outline dimensions symbol dimensions in mil min. nom. max. a 1445 1465 b 535 555 c 145 155 d 125 145 e16 20 f50 70 g 100 h 595 615 i 635 670 0 15 HT23C512 rev. 1.10 8 august 30, 2002

28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 HT23C512 rev. 1.10 9 august 30, 2002

product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 HT23C512 rev. 1.10 10 august 30, 2002
carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 HT23C512 rev. 1.10 11 august 30, 2002

HT23C512 rev. 1.10 12 august 30, 2002 copyright 2002 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science-based industrial park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (sales office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (shanghai) inc. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holmate semiconductor, inc. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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